TSMC Develops Intel-Style Packaging Technology Amid CoWoS Capacity Crunch

What happened

TSMC is developing an EMIB-like packaging technology in partnership with Kinsus Interconnect Technology, according to multiple reports. The project, referred to internally as EMIB-like, adopts Intel's approach of embedding small silicon bridges directly into package substrates rather than using full silicon interposers. Meanwhile, Intel announced its EMIB-T platform achieved a 98% yield rate in mid-July 2026, matching TSMC's CoWoS performance. Intel also revealed major customer wins: Google ordered packaging for over 3 million custom Tensor Processing Units for 2028, Amazon's AWS Trainium 3 is targeting Intel's platform, and MediaTek announced dual-platform support in May 2026. Nvidia is reportedly evaluating Intel's EMIB for a future processor combining four GPU dies, with an estimated 25% Intel / 75% TSMC packaging split for its Feynman GPU around 2028. Both TSMC and Intel shares rallied on the news, rising approximately 7.5% and 13% respectively.

Why it matters

The development signals intensifying competition in advanced chip packaging, a critical bottleneck in AI infrastructure. TSMC's CoWoS capacity is fully sold out through 2026 and into 2027, with lead times exceeding one year and an estimated 20% supply-demand gap in 2026. TSMC is scaling from approximately 35,000 CoWoS wafer starts per month in late 2024 to a projected 130,000 by year-end 2026, yet demand still exceeds supply. Intel's EMIB technology offers advantages for large-scale packages: it currently supports packages exceeding 8 times the reticle limit (versus CoWoS-S's approximately 3.3 times), with roadmaps targeting 12 times by 2028. The embedded-bridge approach reduces costs by eliminating expensive silicon interposers (which represent 40 to 60 percent of total CoWoS package cost), improves thermal performance, and simplifies assembly. For Intel, customer commitments from hyperscalers validate years of investment in packaging technology and represent a potential revenue stream as the company repositions its foundry business. Advanced packaging is projected to reach approximately $69.5 billion by 2029, representing 10 to 15 percent of TSMC's roughly $120 billion annual revenue.

Bigger picture

Advanced chip packaging has become as critical as silicon manufacturing in the AI infrastructure buildout. AI chip designs are approaching physical size limits imposed by lithography equipment (the 858 mm² reticle limit), forcing designers to assemble multi-die systems where packaging format determines final package size and efficiency. TSMC's CoWoS platform dominates high-bandwidth GPU training workloads due to its full silicon interposer providing superior interconnect density and lower latency, which is why Nvidia's flagship Blackwell and Rubin GPUs continue using CoWoS. Intel's EMIB targets cost-sensitive AI ASICs and inference accelerators from hyperscalers like Google and AWS, where package size and cost matter more than absolute peak bandwidth. By developing an EMIB-like alternative, TSMC can offer both high-bandwidth (CoWoS) and large-package cost-efficient (EMIB-like) options within its own supply chain, preventing customers from routing business to Intel's foundry. The competitive dynamic may expand total packaging capacity rather than redistribute market share, as cloud hyperscaler AI infrastructure spending runs at roughly $700 billion for 2026. TSMC is also advancing CoPoS (Chip-on-Panel-on-Substrate) technology using 310 mm × 310 mm panels instead of round 300mm wafers, potentially reaching mass production by 2028. The dual stock rally suggests investors view packaging as a growth market large enough to accommodate multiple winners.

What to watch

Monitor whether TSMC announces specific customers, production timelines, and yield rates for its EMIB-like technology, which would determine how quickly it can relieve CoWoS capacity constraints. Confirmation of Nvidia's packaging strategy for its Feynman GPU architecture would validate whether Intel's EMIB becomes a significant external foundry product or remains limited to niche applications. Track Intel's progress scaling EMIB-T capacity globally across US and Malaysia facilities, and whether additional hyperscaler customers beyond Google and Amazon commit to the platform. TSMC's CoPoS panel-level packaging development and production readiness timeline will indicate the next competitive frontier beyond current bridge-based approaches. Watch for updates on TSMC's CoWoS expansion progress toward its 130,000 wafer starts per month target and whether the supply-demand gap narrows. Any shifts in Nvidia's packaging allocation between TSMC and Intel for future GPU generations would signal competitive positioning changes in the high-end AI accelerator segment.